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1 ltc3564 3564f high efficiency: up to 96% very low quiescent current: only 20 a 1.25a output current 2.5v to 5.5v input voltage range 2.25mhz constant frequency operation no schottky diode required low dropout operation: 100% duty cycle 0.6v reference allows low output voltages shutdown mode draws 1 a supply current current mode operation for excellent line and load transient response overtemperature protected low profile (1mm) thinsot tm and 6-lead (2mm 3mm) dfn packages the ltc ? 3564 is a high efficiency monolithic synchro- nous buck regulator using a constant frequency, current mode architecture. supply current during operation is only 20 a, dropping to 1 a in shutdown. the 2.5v to 5.5v input voltage range makes the ltc3564 ideally suited for single li-ion battery-powered or 3.3v to 5v input voltage applications. 100% duty cycle provides low drop- out operation, extending battery life in portable systems. automatic burst mode ? operation increases efficiency at light loads, further extending battery runtime. switching frequency is internally set at 2.25mhz, allowing the use of small surface mount inductors and capacitors. the internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. low output voltages are easily supported with the 0.6v feed- back reference voltage. the ltc3564 is available in low profile (1mm) thinsot and 6-lead (2mm 3mm) dfn packages. cellular telephones wireless and dsl modems digital still cameras media players portable instruments point of load regulation 2.25mhz, 1.25a synchronous step-down regulator features descriptio u applicatio s u typical applicatio u , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6580258, 6304066, 6498466, 6611131. v in c in 22 f cer v in ltc3564 run 1.1 h 22pf 634k 316k 3564 ta01a sw v fb gnd c out 22 f cer v out 1.8v output current (ma) 0.1 40 efficiency (%) power loss (w) 50 60 70 8 0 1 10 100 1000 10000 3564 ta01b 30 20 10 0 90 100 0.0001 0.001 0.01 0.1 0.00001 1 10 v out = 1. 8 v v in = 2.7v v in = 3.6v v in = 4.2v
2 ltc3564 3564f input supply voltage .................................. e 0.3v to 6v run, v fb voltages ..................................... e 0.3v to v in sw voltage (dc) ......................... e 0.3v to (v in + 0.3v) (note 1) operating junction temperature range (notes 2, 3, 6) ...................................... e 40 c to 125 c storage temperature range ................ e 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c absolute axi u rati gs w ww u symbol parameter conditions min typ max units i vfb feedback current 30 na v fb regulated feedback voltage (note 4) 0.5880 0.6 0.6120 v ) v fb reference voltage line regulation v in = 2.5v to 5.5v (note 4) 0.04 0.4 %/v i pk peak inductor current v in = 3v, v fb = 0.5v, duty cycle < 35% 1.5 2.0 2.5 a v loadreg output voltage load regulation 0.5 % v in input voltage range 2.5 5.5 v the denotes specifications which apply over the full operating junction temperature range, otherwise specifications are t a = 25 c. v in = 3.6v unless otherwise specified. electrical characteristics t jmax = 125 c, v ja = 215 c/ w, v jc = 50 c/ w v fb 1 gnd 2 v in 3 5 run 4 sw top view s5 package 5-lead plastic tsot-23 top view run sgnd v fb sw pgnd v in dcb package 6-lead (2mm 3mm) plastic dfn 4 5 7 6 3 2 1 t jmax = 125 c, v ja = 64 c/ w, v jc = 10.6 c/ w exposed pad (pin 7) is sgnd, must be soldered to pcb pi co figuratio uuu lead free finish tape and reel part marking* package description temperature range ltc3564es5#pbf ltc3564es5#trpbf ltcyj 5-lead plastic tsot-23 e40 c to 125 c ltc3564is5#pbf ltc3564is5#trpbf ltcyj 5-lead plastic tsot-23 e40 c to 125 c ltc3564edcb#pbf ltc3564edcb#trpbf ldtq 6-lead (2mm 3mm) plastic dfn e40 c to 125 c ltc3564idcb#pbf ltc3564idcb#trpbf ldtq 6-lead (2mm 3mm) plastic dfn e40 c to 125 c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ order i for atio uu w
3 ltc3564 3564f symbol parameter conditions min typ max units i s input dc bias current (note 5) active mode v fb = 0.5v or v out = 90%, i load = 0a 300 400 a sleep mode v fb = 0.62v or v out = 103%, i load = 0a 20 35 a shutdown v run = 0v, v in = 4.2v 0.1 1 a f osc oscillator frequency v fb = 0.6v or v out = 100% 1.8 2.25 2.7 mhz r pfet r ds(on) of p-channel fet s5 package 0.15 0.2 dcb package 0.15 r nfet r ds(on) of n-channel fet s5 package 0.15 0.2 dcb package 0.15 i lsw sw leakage v run = 0v, v sw = 0v or 5v, v in = 5v 0.01 1 a v run run threshold 0.3 1 1.5 v i run run leakage current 0.01 1 a t softstart soft-start time v fb from 10% to 90% full scale 0.6 0.9 1.2 ms the denotes specifications which apply over the full operating junction temperature range, otherwise specifications are t a = 25 c. v in = 3.6v unless otherwise specified. electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliabilty and lifetime. note 2: the ltc3564e is guaranteed to meet performance specifications from 0 c to 125 c junction temperature. specifications over the C40 c to 125 c operating junction termperature range are assured by design, characterization and correlation with statistical process controls. the ltc3564i is guaranteed over the full C40 c to 125 c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125 c. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc3564es5: t j = t a + (p d )(215 c/w) ltc3564edcb: t j = t a + (p d )(64 c/w) note 4: the ltc3564 is tested in a proprietary test mode. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability.
4 ltc3564 3564f efficiency vs input voltage efficiency vs output current efficiency vs output current reference voltage vs temperature oscillator frequency vs temperature t a = 25 c, v in = 3.6v, unless otherwise specified. typical perfor a ce characteristics uw frequency variation vs v in load regulation line regulation r ds(on ) vs input voltage input voltage (v) 2.5 40 efficiency (%) 50 60 70 8 0 100 3.0 3.5 4.0 4.5 3564 g01 5.0 5.5 90 i out = 100ma v out = 1. 8 v i out = 1.25a i out = 10ma i out = 1ma i out = 0.1ma output current (ma) 0.1 40 efficiency (%) 50 60 70 8 0 1 10 100 1000 10000 3564 g02 30 20 10 0 90 100 v out = 1.2v v in = 2.7v v in = 3.6v v in = 4.2v output current (ma) 0.1 40 efficiency (%) 50 60 70 8 0 1 10 100 1000 10000 3564 g04 30 20 10 0 90 100 v out = 1.5v v in = 2.7v v in = 3.6v v in = 4.2v temperature ( c) C50 reference voltage (mv) 605 610 615 25 75 3564 g04 600 595 C25 0 50 100 125 590 5 8 5 temperature ( c) C50 oscillator frequency (mhz) 2.35 25 3564 g05 2.20 2.10 C25 0 50 2.05 2.00 2.40 2.30 2.25 2.15 75 100 125 v in (v) 2.5 6 4 2 0 C2 C4 C6 C 8 4.0 5.0 3564 g06 3.0 3.5 4.5 5.5 frequency variation (%) output current (ma) 0 v out error (%) 0.50 0.75 1.00 600 1000 3564 g07 0.25 0 200 400 8 00 1200 1400 C0.25 C0.50 v out = 1. 8 v input voltage (v) 2.5 C0.6 v out error (%) C0.4 C0.2 0 0.2 0.6 3.0 3.5 4.0 4.5 3564 g0 8 5.0 5.5 0.4 v out = 1. 8 v i load = 400ma input voltage (v) 2.5 0 r ds(on) ( ) 0.05 0.10 0.15 0.20 0.25 3.0 3.5 4.0 4.5 3564 g09 5.0 5.5 main switch synchronous switch
5 ltc3564 3564f supply current vs supply voltage supply current vs temperature switch leakage vs temperature switch leakage vs input voltage typical perfor a ce characteristics uw temperature ( c) C50 switch leakage (na) 400 500 600 25 75 3564 g13 300 200 C25 0 50 100 125 100 0 synchronous switch main switch temperature ( c) C50 supply current ( a) 30 35 40 25 75 3564 g12 25 20 C25 0 50 100 125 15 10 v in = 3.6v run = v in i load = 0a input voltage (v) 0 0 switch leakage (pa) 500 1000 1500 2000 2500 1 234 3564 g14 56 run = 0v synchronous switch main switch t a = 25 c, v in = 3.6v, unless otherwise specified. r ds(on) vs temperature temperature ( c) C50 r ds(on) ( ) 0.20 0.25 0.30 25 75 3564 g10 0.15 0.10 C25 0 50 100 125 0.05 0 main switch synchronous switch supply voltage (v) 2.5 10 supply current ( a) 15 20 25 30 35 3.0 3.5 4.0 4.5 3564 g11 5.0 5.5
6 ltc3564 3564f load step load step typical perfor a ce characteristics uw i load 1a/div i l 1a/div v out 100mv/div ac coupled 20 s/div v in = 3.6v v out = 1.8v i load = 50ma to 1.25a 3564 g19 i l 1a/div i load 1a/div v out 100mv/div ac coupled 20 s/div v in = 3.6v v out = 1.8v i load = 0.25a to 1.25a 3564 g20 start-up from shutdown start-up from shutdown load step run 2v/div i l 500ma/div v out 1v/div 400 s/div v in = 3.6v v out = 1.8v i load = 0ma 3564 g16 v out 1v/div i l 1a/div run 2v/div 400 s/div v in = 3.6v v out = 1.8v i load = 1.25a 3564 g17 i load 1a/div i l 1a/div v out 100mv/div ac coupled 20 s/div v in = 3.6v v out = 1.8v i load = 0a to 1.25a 3564 g18 burst mode operation sw 2v/div i l 200ma/div v out 50mv/div ac coupled 2.5 s/div v in = 3.6v v out = 1.8v i load = 40ma 3564 g15 t a = 25 c, v in = 3.6v, unless otherwise specified.
7 ltc3564 3564f v fb (pin 1/pin 4) : feedback pin. receives the feedback voltage from an external resistive divider across the out- put. gnd (pin 2/na): ground pin. v in (pin 3/pin 3): main supply pin. must be closely decoupled to gnd, pin 2, with a 10 f or greater ceramic capacitor. sw (pin 4/pin 1): switch node connection to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. run (pin 5/pin 6): run control input. forcing this pin above 1.5v enables the part. forcing this pin below 0.3v shuts down the device. in shutdown, all functions are disabled drawing <1 a supply current. do not leave run floating. pgnd (na/pin 2): main power ground pin. connect to the (C) terminal of c out , and (C) terminal of c in . sgnd (na/pins 5, 7): the signal ground pin. all small signal components and compensation components should be connected to this ground (see board layout consider- ations.) pi fu ctio s uuu (s5/dcb) fu ctio al diagra uu w + C + C + C ea + C i rcmp + C i comp run osc slope comp osc freq shift 0.6v 0.6v ref shutdown 0.52v 0.65v sleep v in v fb burst v in s r rs latch switching logic and blanking circuit anti- shoot- thru q q r sense sw gnd 3564 fd
8 ltc3564 3564f (refer to functional diagram) main control loop the ltc3564 uses a constant frequency, current mode step-down architecture. both the main (p-channel mosfet) and synchronous (n-channel mosfet) switches are internal. during normal operation, the internal top power mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the current com- parator, i comp , resets the rs latch. the peak inductor current at which i comp resets the rs latch, is controlled by the output of error amplifier ea. when the load current increases, it causes a slight decrease in the feedback voltage, fb, relative to the 0.6v reference, which in turn, causes the ea amplifiers output voltage to increase until the average inductor current matches the new load cur- rent. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator i rcmp , or the beginning of the next clock cycle. burst mode operation the ltc3564 is capable of burst mode operation in which the internal power mosfets operate intermittently based on load demand. in burst mode operation, the peak current of the inductor is set to approximately 180ma regardless of the output load. each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. in between these burst events, the power mosfets and any unneeded circuitry are turned off, reducing the quiescent current to 20 a. in this sleep state, the load current is being supplied solely from the output capacitor. as the output voltage droops, the ea amplifiers output rises above the sleep threshold signal- ing the burst comparator to trip and turn the top mosfet on. this process repeats at a rate that is dependent on the load demand. short-circuit protection when the output is shorted to ground, the inductor current may exceed the maximum inductor peak current if not allowed enough time to decay. to prevent the inductor current from running away, the bottom n-channel mosfet is allowed to stay on for more than one cycle, thereby allowing the inductor current time to decay. dropout operation as the input supply voltage decreases to a value approach- ing the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the p-channel mosfet and the inductor. an important detail to remember is that at low input supply voltages, the r ds(on) of the p-channel switch increases (see typical performance characteristics). therefore, the user should calculate the power dissipation when the ltc3564 is used at 100% duty cycle with low input voltage (see thermal considerations in the applications informa- tion section). slope compensation and inductor peak current slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- tions at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. however, the ltc3564 uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. operatio u
9 ltc3564 3564f the basic ltc3564 application circuit is shown in figure 1. external component selection is driven by the load require- ment and begins with the selection of l followed by c in and c out . inductor selection for most applications, the value of the inductor will fall in the range of 0.47 h to 2.2 h. its value is chosen based on the desired ripple current. large value inductors lower ripple current and small value inductors result in higher ripple currents. higher v in or v out also increases the ripple current as shown in equation 1. a reasonable starting point for setting ripple current is i l = 500ma (40% of 1.25a). = ()( ) ? ? ? ? ? ? ? i fl v v v l out out in 1 1 (1) the dc current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. thus, a 1.5a rated inductor should be enough for most applications (1.25a + 250ma). for better efficiency, choose a low dc-resis- tance inductor. the inductor value also has an effect on burst mode operation. the transition to low current operation begins when the inductor current peaks fall to approximately 300ma. lower inductor values (higher i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy mate- rials are small and dont radiate much energy, but gener- ally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/emi requirements than on what the ltc3564 requires to operate. table 1 shows some typical surface mount inductors that work well in ltc3564 applications. applicatio s i for atio wu u u table 1. representative surface mount inductors manufaturer part number value ( h) max dc current (a) dcr ( m ) height (mm) toko a915ay-1r1m-dc53lc 1.1 3.25 16 3 1070as-1r0n-db3020c 1 1.9 47 2 sumida cdrh4d18c/ld-1r1 1.1 2.1 24 2 cdrh3d14-1r2 1.2 2.2 36 1.5 cr5d11-1r0 1 2.2 40 1.2 cdrh2d18/hp-2r2 2.2 1.6 48 2 fdk mipw3226d0r9m 0.9 1.4 70 1 coilcraft lpo6610-122ml 1.2 2.1 80 1 lps4018-222ml 2.2 2.5 70 1.8 vishay ihlp1616aberr47m01 0.47 5 20 1.2 ihlp1616aber1r0m01 1 4 45 1.2 v in ltc3564 run r1 3564 f01 r2 c f l c in c out sw v in v out v fb gnd figure 1. ltc3564 general schematic
10 ltc3564 3564f c in and c out selection in continuous mode, the source current of the top mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ci vvv v in omax out in out in required i rms ? ? () [] 12 / this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that the capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. always consult the manufac- turer if there is any question. the selection of c out is driven by the required effective series resistance (esr). typically, once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. the output ripple v out is deter- mined by: ? + ? ? ? ? ? ? v i esr fc out l out 1 8 where f = operating frequency, c out = output capacitance and i l = ripple current in the inductor. for a fixed output voltage, the output ripple is highest at maximum input voltage since i l increases with input voltage. aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalum capacitors. these are specially constructed and tested for low esr so they give the lowest esr for a given volume. other capacitor types include sanyo poscap, kemet t510 and t495 series, and sprague 593d and 595d series. consult the manufacturer for other specific recommendations. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. because the ltc3564s control loop does not depend on the output capacitors esr for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. however, care must be taken when ceramic capacitors are used at the input and the output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in , large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. applicatio s i for atio wu u u
11 ltc3564 3564f output voltage programming in the adjustable version, the output voltage is set by a resistive divider according to the following formula: vv r r out =+ ? ? ? ? ? ? 06 1 2 1 . (2) the external resistive divider is connected to the output, allowing remote voltage sensing as shown in figure 2. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical character- istics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge, dq, moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in continuous mode, the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in ltc3564 circuits: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in figure 3. applicatio s i for atio wu u u figure 3. power lost vs load current figure 2. setting the ltc3564 output voltage load current (a) 0.1 0.0001 power loss (w) 0.01 1 1 10 100 1000 10000 3564 f03 0.001 0.1 v out = 1.2v v out = 1.5v v out = 1. 8 v v in = 3.6v v fb gnd ltc3564 0.6v v out 5.5v r2 r1 3564 f02
12 ltc3564 3564f the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteris- tics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses which generally account for less than 2% total additional loss. thermal considerations in most applications the ltc3564 does not dissipate much heat due to its high efficiency. but, in applications where the ltc3564 is running at high ambient tempera- ture with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maxi- mum junction temperature of the part. if the junction temperature reaches approximately 150 c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3564 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera- ture rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. as an example, consider the ltc3564 in dropout at an input voltage of 2.7v, a load current of 1.2a and an ambient temperature of 70 c. from the typical perfor- mance graph of switch resistance, the r ds(on) of the p-channel switch at 70 c is approximately ~0.2 . there- fore, power dissipated by the part is: p d = i load 2 ? r ds(on) = 288mw for the sot-23 package, the ja is 215 c/ w. thus, the junction temperature of the regulator is: t j = 70 c + (0.288)(215) = 131.9 c which is above the maximum junction temperature of 125 c. note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (r ds(on) ). checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( i load ? esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out , which generates a feedback error signal. the regulator loop then acts to return v out to its steady- state value. during this recovery time v out can be moni- tored for overshoot or ringing that would indicate a stability problem. for a detailed explanation of switching control loop theory, see application note 76. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 ? c load ). thus, a 10 f capacitor charging to 3.3v would require a 250 s rise time, limiting the charging current to about 130ma. applicatio s i for atio wu u u
13 ltc3564 3564f figure 4a. ltc3564 tsot-23 layout diagram applicatio s i for atio wu u u figure 4b. ltc3564 dfn layout diagram v fb ltc3564 gnd v in l1 r2 r1 c fwd bold lines indicate high current path v out v in 3564 f04a 4 5 1 3 + C 2 run sw c out c in sw ltc3564 pgnd v in r1 c fwd bold lines indicate high current path v in v out 3564 f04b 4 6 5 1 3 + C 2 run sgnd v fb c out c in r2 l1
14 ltc3564 3564f applicatio s i for atio wu u u figure 5a. ltc3564 tsot-23 suggested layout figure 5b. ltc3564 dfn suggested layout ltc3564 gnd 3564 f05a pin 1 v out v in via to v out sw via to v in via to gnd c out c in l1 r2 c fwd r1 3564 f05b v out pgnd v in v fb via to v out sw via to v in c in c out l1 r2 c fwd r1 4 5 7 6 3 2 1 sgnd
15 ltc3564 3564f pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3564. these items are also illustrated graphically in figures 4 and 5. check the following in your layout: 1. the power traces, consisting of the gnd trace, the sw trace and the v in trace should be kept short, direct and wide. 2. does the v fb pin connect directly to the feedback resistors? the resistive divider r1/r2 must be con- nected between the (+) plate of c out and ground. 3. does the (+) plate of c in connect to v in as closely as possible? this capacitor provides the ac current to the internal power mosfets. 4. keep the switching node, sw, away from the sensitive v fb node. 5. keep the (C) plates of c in and c out as close as possible. design example as a design example, assume the ltc3564 is used in a single lithium-ion battery-powered cellular phone application. the v in will be operating from a maximum of 4.2v down to about 2.7v. the load current requirement is a maximum of 1.25a but most of the time it will be in standby mode, requiring only 2ma. efficiency at both low figure 6a. typical application figure 6b. efficiency vs output current and high load currents is important. output voltage is 2.5v. with this information we can calculate l using equation (1), l fi v v v l out out in = () () ? ? ? ? ? ? ? 1 1 (3) substituting v out = 2.5v, v in = 4.2v, i l = 500ma and f = 2.25mhz in equation (3) gives: l= 2.5v 2.25mhz(500ma) 1 25 42 09 ? ? ? ? ? ? ? = . . . v v h h a 1 h or 1.1 h inductor works well for this application. for best efficiency choose a 1.5a or greater inductor with less than 0. 1 series resistance. c in will require an rms current rating of at least 0.6a ? i load(max) /2 at temperature and c out will require an esr of less than 0.125 . in most cases, a ceramic capacitor will satisfy this requirement. for the feedback resistors, choose r1 = 316k. r2 can then be calculated from equation (2) to be: r v rk out 2 06 1 1 1000 = ? ? ? ? ? ? ? = . figure 6 shows the complete circuit along with its effi- ciency curve. applicatio s i for atio wu u u v in c in ** 22 f cer v in 2.7v to 4.2v ltc3564 run 4 1.1 h* 22pf 1m 316k 3564 f06a 1 3 5 2 sw v fb gnd c out ** 22 f cer v out 2.5v *toko a915ay-1r1m (d53lc series) ** taiyo yuden jmk316bj226ml output current (ma) 70 efficiency (%) 8 0 8 5 95 100 0.1 10 100 1000 3564 f06b 60 1 90 75 65 v out = 2.5v v in = 2.7v v in = 3.6v v in = 4.2v
16 ltc3564 3564f v in c in ** 10 f cer v in 2.7v to 5.5v ltc3564 run 3 1 h* 22pf 806k 402k 3564 ta02a 5 4 1 2 sw v fb gnd c out ? 22 f cer v out 1.8v *murata lqh32cn2r2m33 ** taiyo yuden jmk316bj106ml ? taiyo yuden jmk316bj226ml-br single li-ion 1.8v/1.25a regulator for high efficiency and small footprint output current (ma) 0.1 40 efficiency (%) 50 60 70 8 0 100 1 10 1000 10000 3564 ta02b 30 20 10 0 90 100 v out = 1. 8 v v in = 2.7v v in = 3.6v v in = 4.2v i l 1a/div i load 1a/div v out 100mv/div ac coupled 20 s/div v in = 3.6v v out = 1. 8 v i load = 100ma to 1.25a 3564 ta02c typical applicatio s u
17 ltc3564 3564f single li-ion 1.5v/1.25a regulator for high efficiency and low profile, <1mm height v in c in ** 10 f cer v in 2.7v to 5.5v ltc3564 run 3 0.9 h* 22pf 604k 402k *fdk mipw3226d0r9m **taiyo yuden jmk107bj106m a 3564 ta03a 5 4 1 2 sw v fb gnd c out ** 10 f 2 cer v out 1.5v output current (ma) 0.1 40 efficiency (%) 50 60 70 8 0 100 1 10 1000 10000 3564 ta03b 30 20 10 0 90 100 v out = 1.5v v in = 2.7v v in = 3.6v v in = 4.2v i l 1a/div i load 1a/div v out 100mv/div ac coupled 20 s/div v in = 3.6v v out = 1.5v i load = 0.3a to 1.25a 3564 ta04c typical applicatio s u
18 ltc3564 3564f s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635) package descriptio u 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 typ 5 plcs (note 3) datum a 0.09 C 0.20 (note 3) s5 tsot-23 0302 rev b pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
19 ltc3564 3564f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u dcb package 6-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1715 rev a) 3.00 0.10 (2 sides) 2.00 0.10 (2 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (tbd) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.35 0.10 (2 sides) 1 3 6 4 pin 1 bar top mark (see note 6) 0.200 ref 0.00 C 0.05 (dcb6) dfn 0405 0.25 0.05 0.50 bsc pin 1 notch r0.20 or 0.25 45 chamfer 0.25 0.05 1.35 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.70 0.05 3.55 0.05 package outline 0.50 bsc
20 ltc3564 3564f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com lt 0608 ? printed in usa ? linear technology corporation 2008 related parts part number description comments ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20 a, dc/dc converters i sd = <1 a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20 a, dc/dc converters i sd = <1 a, thinsot package ltc3407/ltc3407-2 dual 600ma/800ma (i out ), 1.5mhz/2.25mhz, 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40 a, synchronous step-down dc/dc converters i sd = <1 a, ms10e, dfn packages ltc3409 600ma (i out ), 1.7mhz/2.6mhz, synchronous 96% efficiency, v in : 1.6v to 5.5v, v out(min) = 0.6v, i q = 65 a, step-down dc/dc converter i sd = <1 a, dfn package ltc3410/ltc3410b 300ma (i out ), 2.25mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 26 a, dc/dc converters i sd = <1 a, sc70 package ltc3411 1.25a (i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60 a, dc/dc converter i sd = <1 a, ms10, dfn packages ltc3412 2.5a (i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60 a, dc/dc converter i sd = <1 a, tssop-16e package ltc3441/ltc3442 1.2a (i out ), 2mhz, synchronous buck-boost 95% efficiency, v in : 2.4v to 5.5v, v out(min) : 2.4v to 5.25v, ltc3443 dc/dc converters i q = 50 a, i sd = <1 a, dfn package ltc3531/ltc3531-3 200ma (i out ), 1.5mhz, synchronous buck-boost 95% efficiency, v in : 1.8v to 5.5v, v out(min) : 2v to 5v, i q = 16 a, ltc3531-3.3 dc/dc converters i sd = <1 a, thinsot, dfn packages ltc3532 500ma (i out ), 2mhz, synchronous buck-boost 95% efficiency, v in : 2.4v to 5.5v, v out(min) : 2.4v to 5.25v, dc/dc converter i q = 35 a, i sd = <1 a, ms10, dfn packages ltc3542 500ma (i out ), 2.25mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 0.6v, dc/dc converter i q = 26 a, i sd = <1 a, thinsot, 2 2 dfn packages ltc3548/ltc3548-1 dual 400ma/800ma (i out ), 2.25mhz, synchronous 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40 a, ltc3548-2 step-down dc/dc converters i sd = <1 a, ms10e, dfn packages ltc3560 800ma (i out ), 2.25mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 16 a, dc/dc converters i sd = <1 a, thinsot package ltc3561 1.25a (i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 240 a, dc/dc converter i sd = <1 a, dfn package

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